This chapter connects system-on-chip (SoC) realities—caches, cores, interconnects—to Cloudflare’s edge model, so you can reason from cycles and cache lines up to packets and serverless workloads.
Hardware execution context at the edge
- Modern edge servers use multi-socket, multi-core CPUs with SMT; NUMA awareness matters for memory locality.
- Workers isolate request handlers; startup costs are far lower than VM boots; think microsecond to millisecond scheduling, not seconds.
- Perf levers: CPU frequency scaling, cache residency (I/D-cache warmth), branch predictability, syscalls and context switches minimization.
Chip Architect Note: Treat each Worker invocation as a short-lived compute kernel sensitive to code size, branch predictability, and memory locality. Smaller bundles and fewer dependencies yield better i-cache behavior.
Network path and queuing
- NIC → kernel networking stack → user-space runtime; zero-copy and offloads reduce latency and CPU.
- BPF/WAF/filtering at the edge influences cache pressure and branch behavior on hot paths.
- Anycast and load-balancing distribute flows across PoPs; per-connection state should be minimized or stored in edge services.
Chip Architect Note: Think of PoPs as NUMA domains across the Internet. Keep state sharded (KV/D1) and leverage cache-control to avoid needless recompute at distant PoPs.
Data movement economics
- KV reads: global, eventually consistent, ideal for config and caches.
- D1: relational semantics; co-locate data by region when needed.
- R2: object storage; rely on CDN semantics and ETags for efficient delivery.
Chip Architect Note: Optimize for fewer bytes moved. Compress text (Brotli), cache aggressively with immutable assets, and precompute frequently used responses.